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dsPIC30F1010/202X

DS70178C-page 182

Preliminary

2006 Microchip Technology Inc.

16.6

Reverse Conversion Order

The ORDER control bit in the ADCON register, when

set, reverses the order of the input pair conversion pro-

cess. Normally (ORDER = 0), the even numbered

input of an input pair is converted first and then the odd

numbered input is converted. If ORDER = 1, the odd

numbered input pin of an input pair is converted first,

followed by the even numbered pin.

This feature is useful when using voltage control

modes and using the early interrupt capability

(EIE = 1). These features enable the user to minimize

the time period from actual acquisition of the feedback

(ADC) data to the update of the control output (PWM).

This time from input to output of the control system

determines the overall stability of the control system.

16.7

Simultaneous and Sequential

Sampling in a pair

The inputs that have dedicated Sample and Hold

(S&H) circuits are sampled when their specified trigger

events occur. The inputs that share the common sam-

ple and hold circuit are sampled in the following

manner:

If the SEQSAMP bit = 0, and the common

(shared) sample and hold circuit is NOT busy,

then the shared S&H will sample their specified

input at the same time as the dedicated S&H.

This action provides “Simultaneous” sample and

hold functionality.

If the SEQSAMP bit = 0, and the shared S&H is

currently busy with a conversion in progress,

then the shared S&H will sample as soon as

possible (at the start of the new conversion

process for the pair).

If the SEQSAMP bit = 1, then the shared S&H

will sample at the start of the conversion process

for that input. For example: If the ORDER bit = 0

the shared S&H will sample at the start of the

conversion of the second input. If ORDER = 1,

then the shared S&H will sample at the start of

the conversion for the first input.

The SEQSAMP bit is useful for some applica-

tions that want to minimize the time from a

sample event to the conversion of the sample.

When SEQSAMP = 0, the logic attempts to take

the samples for both inputs of a pair at the same

time if the resources are available. The user can

often ensure that the ADC will not be busy with

a prior conversion by controlling the timing of the

trigger signals that initiate the conversion

processes.

16.8

Group Interrupt Generation

The ADC module provides a common or “Group” inter-

rupt request that is the OR of all of the enabled interrupt

sources within the module. Each CPC register has two

IRQENx bits, one for each analog input pair. If the

IRQEN bit is set, an interrupt request is made to the

interrupt controller when the requested conversion is

completed. When an interrupt is generated, an asso-

ciated PxRDY bit in the ADSTAT register is set. The

PxRDY bit is cleared by the user. The user’s software

can examine the ADSTAT register’s PxRDY bits to

determine if additional requested conversions have

been completed.

The group interrupt is useful for applications that use a

common software routine to process ADC interrupts for

multiple analog input pairs. This method is more

traditional in concept.

Note:

The user must clear the IFS bit associated

with the ADC in the interrupt controller

before the PxRDY bit is cleared. Failure to

do so may cause interrupts to be lost. The

reason is that the ADC will possibly have

another interrupt pending. If the user

clears the PxRDY bit first, the ADC may

generate another interrupt request, but if

the user then clears the IFS bit, the

interrupt request will be erased.

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